A multi-phase DC-DC power converter is widely applied in different electronic devices. The technology of a constant on-time voltage regulator is applied in a power converter. Generally speaking, when a feedback voltage is smaller than a reference voltage, a constant on time (COT) voltage regulator may turn on a primary switch in a fixed period, and the constant on time voltage regulator may adjust a turn-off period of the primary switch, so as to provide a stable output voltage.
FIG. 1 is a schematic circuit diagram of a multi-phase DC-DC power converter in the prior art. Please refer to FIG. 1. A multi-phase DC-DC power converter 100 includes a plurality of output stage circuits 1021 to 102N, a pulse width modulation (PWM) controller 120, a resistor RESR, and an output capacitor C1, in which N is a positive integer. The multi-phase DC-DC power converter 100 converts an input voltage VIN received by an input node Nin into an output voltage VOUT. The multi-phase DC-DC power converter 100 includes 2N transistors MU1 to MUN and ML1 to MLN, N inductors L1 to LN, N control units 1101 to 110N, and a PWM controller 120. The transistors MU1 to MUN are coupled between the input node Nin and nodes N1 to NN, respectively, whereas the transistors ML1 to MLN are coupled between the nodes N1 to NN and the ground GND, respectively. The transistors MU1 to MUN and the transistors ML1 to MLN are N-type transistors and may be used as switches. In other different applications, the transistors MU1 to MUN and the transistors ML1 to MLN may also be P-type transistors or may be P-type transistors and N-type transistors at the same time. The control units 1101 to 110N receive PWM signals SPWM1 to SPWMN provided by the PWM controller 120, and control whether to turn on the transistors MU1 to MUN and the transistors ML1 to MLN according to the PWM signals SPWM1 to SPWMN. The inductors L1 to LN are coupled between the nodes N1 to NN and an output node Nout, respectively, in which the output voltage VOUT is output to a load 200 through the output node Nout. In addition, the output capacitor C1 is coupled between the output node Nout and the ground GND, in which the resistor RESR represents to output an equivalent series resistance (ESR) of the capacitor C1.
As shown in FIG. 1, the PWM controller 120 includes a ramp generator 130, a PWM generator 140, a compensation unit 150, an error amplifier 160, a comparator 170, a phase channel current sensor 180, and a phase channel selector 190. The error amplifier 160 receives a reference voltage VREF and an output voltage VOUT, and generates an error signal VERR according to a voltage difference between the reference voltage VREF and the output voltage VOUT. The compensation unit 150 is coupled between the comparator 170 and an output terminal of the error amplifier 160, and the compensation unit 150 is used for compensating for the error signal VERR. The compensation unit 150 includes a resistor 152 and capacitors 154 and 155, in which the resistor 152 is coupled to the output terminal of the error amplifier 160, the capacitor 154 is coupled between the resistor 152 and the ground GND, and the capacitor 155 is coupled between the output terminal of the error amplifier 160 and the ground GND. After the compensation for the error signal VERR is completed, the comparator 170 compares the error signal with a ramp signal SRAMP provided by the ramp generator 130, so as to generate a trigger signal STR. Next, the PWM generator 140 and the phase channel selector 190 generate PWM signals SPWM1 to SPWMN according to the trigger signal STR, the input voltage VIN, and the output voltage VOUT. The ramp generator 130 generates the ramp signal SRAMP only according to the PWM signals SPWM1 to SPWMN, the input voltage VIN, and the output voltage VOUT. The phase channel current sensor 180 senses currents I1 to IN flowing through the inductors L1 to LN, and after calculation, the error currents IB1 to IBN between all channels are imported into the PWM generator 140, and the PWM generator 140 is used for adjusting the duty cycles of the PWM signals SPWM1 to SPWMN.
However, in the measures in the prior art, the PWM signals SPWM1 to SPWMN are unable to partially overlap each other, resulting in a slow transient response. FIG. 2 is a schematic timing diagram of a multi-phase DC-DC power converter 100 in two phase operations. Please refer to FIG. 1 and FIG. 2 together. In two phase operations, a PWM generator 140 generates a pulse wave signal SPWM0, a phase channel selector 190 forms odd-numbered pulse waves of the pulse wave signal SPWM0 into a PWM signal SPWM1 and forms even-numbered pulse waves of the pulse wave signal SPWM0 into another PWM signal SPWM2, and as the two PWM signals SPWM1 and SPWM2 are separated by a minimum off time, a waveform of the PWM signal SPWM1 is unable to partially overlap a waveform of the PWM signal SPWM2 at a logic high level. As a minimum off time is required to separate PWM signals in a conventional architecture, the application of the multi-phase DC-DC power converter 100 at a high duty cycle is greatly limited.